The present invention relates to variable-capacitance capacitors.
It is known in the art that capacitors, for example corresponding to a reverse-biased junction, have a capacitance which progressively decreases as the voltage there across increases.
Capacitors of this type are for example described in patent GB-A-2305002 of Hewlett-Packard, and illustrated in FIG. 1. Their capacitance-vs-voltage curve is shown in FIG. 2.
FIG. 1 shows a substrate comprising an upper N-type region 1 and a lower N+ type region 2 coated with a metallization 3 connected to a terminal A. The upper surface of the substrate comprises portions in relief 5 separated by recesses 6. An insulating region 7 is formed at the top of relieves 5. A P-type region 8 is formed on the lateral walls of area in relief 5 as well as at the bottom of recesses 6. A conductive layer 9 is formed over the entire upper surface and is coated with a metallization 10 connected to a terminal B.
When a positive voltage is applied on terminal A with respect to terminal B, the PN junction between region 8 and substrate 1 or portion 5 in relief is reverse biased and corresponds to a capacitor.
FIG. 2 shows the variation of capacitance C of the capacitor thus formed as the voltage increases. For small values of voltage VAB, capacitance C is substantially proportional to the perimeter of the elementary capacitor pattern. Indeed, the capacitance per surface area unit of the upper part of the structure shows little difference with the capacitance per surface area unit of a junction, due to the fact that the semiconductor part in relief is lightly doped. As the space charge area extends, the capacitance progressively decreases until, at the time when the space charge areas join, it can be considered that the capacitance of the area in relief is inhibited, that is, its contribution to the value of the capacitance disappears. For a threshold value VT of the voltage, the capacitance of a pattern then passes from a state where it is substantially proportional to the perimeter of a relief to a state where it is proportional to the pitch of a pattern. A capacitor having a capacitance which varies progressively during a first phase, then drops for a threshold voltage VT is thus obtained. However, as shown in FIG. 2, most of the capacitance drop is progressive, and the xe2x80x9cswitchedxe2x80x9d portion only corresponds to a small part of the total capacitance variation.
An object of the present invention is to provide a capacitor having a capacitance which abruptly decreases when the voltage thereacross exceeds a predetermined threshold.
To achieve this object, the present invention provides a capacitor with a variable capacitance comprising a periodic structure of areas in relief separated by recesses formed in a semiconductor substrate of a first doping type, in which the walls of the areas in relief and the bottom of the recesses are coated with a conductive layer, the substrate being connected to a first terminal of the capacitor and the conductive layer to a second terminal of the capacitor, in which at least the bottom of the recesses or the side of the areas in relief comprises regions of the second doping type, the pitch of the portions in relief being selected so that the space charge areas linked to the regions of the second doping type join when the voltage difference between said terminals exceeds a determined threshold. The areas which do not comprise the regions of the second doping type are coated with an insulator and a heavily-doped region of the conductivity type of the substrate is formed under the insulator.
According to an embodiment of the present invention, the conductive layer comprises a polysilicon layer of the second doping type coated with a metallization.
According to an embodiment of the present invention, the areas in relief form ribs.
According to an embodiment of the present invention, the areas in relief and the recesses form a multicellular structure.
According to an embodiment of the present invention, the bottom of the recesses as well as the lateral walls of the areas in relief comprise a region of the second doping type.
According to an embodiment of the present invention, the bottom of the recesses comprises a region of the second doping type while the lateral walls and the upper part of each area in relief are coated with a dielectric layer, the areas in relief being heavily doped.
The present invention also aims at a use of the above-mentioned capacitor in a circuit likely to exhibit across the capacitor a value greater or smaller than said threshold voltage.
According to an embodiment of the present invention, the capacitor comprises at its periphery a heavily-doped isolating wall of the second conductivity type extending from the upper surface to the lower surface of the substrate, connected to said conductive layer and distant from the limit of the lower surface metallization by a distance sufficient to hold a desired voltage.
According to an embodiment of the present invention, on the lower surface side of the substrate, a silicon oxide layer is deposited at the component periphery beyond the lower surface metallization.
The present invention also aims at the use of the above-mentioned capacitor in a circuit likely to exhibit across the capacitor a value greater or smaller than said threshold voltage.